For the Java statements on the left, provide the corresponding MIPS assembly code in the corresponding space on the right.

Exercise I. Translating from Java Language to MIPS Assembly (5*3= 15pts)
For the Java statements on the left, provide the corresponding MIPS assembly code in the corresponding space on the right. Assume f, g, and j are assigned to registers $s0, $s1, and $s2 respectively, and h is assigned to register $v0. Also assume that the starting address of the array A (which is an array of 15 words) is in register $ra
C statements MIPS Assembly code
f = (g + h) + (j +13)
A[12] = h + A[8]
if (j !=h ) f = f + 1;
f = g + h;
Exercise II (2.5*4 = 10 pts)
We wish to compare two systems S1 and S2. The table below presents measurements for the two systems when running
two programs, Program 1 and Program 2.
System 1 System 2
Program ExT (sec) IC ExT (sec) IC
1 6 12x106 8 10x106
2 10 6
1. If the clock rate of system S1 is 4 MHz and the clock rate for system S2 is 6 MHz, find CPI For each
system when running Program 1
CPI for S1 = ______________
CPI for S2 = ______________
2. Assuming the CPI for each system when running Program 2 is the same as it is when running Program 1, find
the instruction count (IC) for each system when running Program 2
IC for S1 = ______________
IC for S2 = ______________
Exercise III (5*3 = 15 pts)
Consider a pipelined execution of the following program segment in which the instruction labeled “Beg” starts at
memory address (2040)10.All registers used contain 0 initially.
Beg: add $8, $9, $10
beq $5, $6, Nex
lw $7, 30($13)
sw $14, 48($15)
Nex : and $11, $12, $13
1. Show the state of the 5-stage pipeline (i.e. the “pipelined execution representation”) for the
instructions above.
2. Assume the time for stages is 100ps for register read or write, and 200ps for other stages. Compute the
total time required for each of the instructions used in the program segment above.
3. Compare the total execution time for non-pipelined and pipelined execution of the above program segment:
Non-pipeline design = ______________ ps
Pipelined design = ______________ ps
_________________ design is _________ times faster
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